Synthesizes, optimizes, minimizes, and maps design logic to device resources. Reports outdated IP that require upgrade. Identifies the status and version of IP components in the project.
1.14 map viewer pro#
Intel Quartus Prime Pro Edition User Guides Intel Quartus Prime Pro Edition User Guide Design Compilation Archives Reducing Compilation Time Revision History
Identifying Routing Congestion with the Chip Planner Use Appropriate Coding Style to Reduce Synthesis Time Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time Reducing Synthesis Time and Synthesis Netlist Optimization Time Strategies to Reduce the Overall Compilation Time VHDL-2019 Conditional Analysis Tool Directives VHDL Input Settings (Settings Dialog Box) Initial Constructs and Memory System Tasks Verilog HDL Input Settings (Settings Dialog Box) Verilog and SystemVerilog Synthesis Support Generating a VQM Netlist for other EDA Tools Viewing Quartus Database File Information Importing a Version-Compatible Compilation Database Exporting a Version-Compatible Compilation Database Step 5: Implement Fast Forward Recommendations Validating Periphery (I/O) after the Plan Stage Analyzing Congestion with Snapshot Viewer Validating Timing Constraints with Snapshot Viewer Analyzing High Fan-out Nets with Snapshot Viewer Analyzing Failing Paths with Snapshot Viewer Concurrent Analysis During Synthesis or Fitting Global Router Wire Utilization Map Report Preserving Signals for Monitoring and Debugging